The present invention generally relates to semiconductor devices and more particularly to a semiconductor device, as well as a fabrication process thereof, that has a reduced area of diffusion regions and hence a reduced parasitic capacitance.
In the semiconductor devices, the parasitic capacitance associated with the diffusion region of the device limits the operational speed of the device. In the MOS transistors, for example, the parasitic capacitance of the diffusion regions, forming the source or drain of the device, limits the operational speed of the device. In the bipolar transistors, too, the parasitic capacitance associated with the diffusion regions limits the operational speed.
In the conventional approach, the area of the diffusion region is reduced as much as possible by employing a strict patterning rule. Such a conventional approach has a problem, however, in that the area of the diffusion region cannot be reduced below a certain limit because of the tolerance needed for the patterning of the contact holes or other patterns.
FIG. 1 shows the structure of a conventional BiMOS hybrid integrated circuit wherein a MOS transistor and a bipolar transistor are provided on a common substrate 31.
Referring to FIG. 1, the substrate 31 includes a first region 31A of the p-type silicon acting as a substrate of the MOS transistor and a second region 31B of the n-type silicon acting as a substrate of the bipolar transistor. On the surface of the substrate 31, a field oxide region 32 is formed as usual for defining the respective device regions of the MOS and bipolar transistors. Further, a source region 33 and a drain region 34 of the n.sup.+ -type are formed in the region 31A of the substrate as usual. On the upper major surface of the region 31A, a gate oxide film 35 of silicon oxide is provided in correspondence to the part between the source region 33 and the drain region 34, and a gate electrode 36 of doped polysilicon is provided on the gate oxide film 35.
On the other hand, a diffusion region 37 of the p-type is formed in the region 31B of the substrate 31 and has formed therein a base 39 of the bipolar transistor. There, the region 31B acts as the collector of the bipolar transistor. Further, a pair of diffusion regions 38 and 38' of the p.sup.+ -type is formed in the region 31B, connected with the bridging region 37 which is directly underneath the base 39, as base contact regions. On the upper major surface of the region 31B, a polysilicon emitter 310 of the n.sup.+ -type is formed directly in contact with the base 37.
Further, silicon oxide layers 311 and 312 are provided to protect the gate electrode 36 and the emitter 310 as well as the surface of the substrate 31. In such a structure, the operational speed of the device increases when the parasitic capacitance associated with the diffusion regions forming the source, drain, or base is reduced, and the parasitic capacitance can be reduced by reducing the size of the diffusion regions.
In the structure of FIG. 1, there exist at least the following factors that prevent the satisfactory reduction of the area of the diffusion regions. First, the size "a" of the contact hole formed in the oxide protection film 312 for electric contact between the diffusion region and an interconnection electrode, has to be set larger than a predetermined limit that is determined by the resolution of the exposure process. Second, there must be a tolerance designated in FIG. 1 by "b" and "c" at both sides of the contact hole such that the contact hole does not expose the field oxide region 32 or the electrode 36 even when there is a deviation in the alignment of the exposure patterns. A similar problem occurs also in the bipolar transistor.
FIG. 2 shows another conventional hybrid integrated circuit that includes both a MOS transistor and a bipolar transistor on a common substrate 41 of silicon.
Referring to FIG. 2, the substrate 41 includes a first region 41A of the p-type silicon acting as a substrate of the MOS transistor and a second region 41B of the n-type silicon acting as a substrate as well as the collector of the bipolar transistor. On the surface of the substrate 41, a field oxide region 42 is formed as usual for defining the respective device regions of the MOS and bipolar transistors. Further, a source region 43 and a drain region 44 of the n.sup.+ -type are formed in the region 41A of the substrate as usual.
On the region 41A, a polysilicon electrode layer is provided, extending along the upper major surface thereof and patterned to form a first polysilicon pattern 46 and a second polysilicon pattern 47 respectively in contact with the source region 43 and the drain region 44. Thereby, the surface of the silicon substrate 41 is exposed in correspondence to a part located between the first polysilicon pattern 46 and the second polysilicon pattern 47. Further, the polysilicon patterns 46 and 47 are covered by a thin silicon oxide film 48, and contact holes are formed on the silicon oxide film 48 in correspondence to the field oxide region 42. Furthermore, the exposed part of the substrate 41 located between the polysilicon patterns 46 and 47 is covered by the silicon oxide film 45 that act as a gate oxide film, and a gate electrode 49 of doped polysilicon is provided on the gate oxide film 45.
In the bipolar transistor, on the other hand, a diffusion region 410 of the p-type is formed in the region 41B of the substrate 41 and has formed therein a base 412 of the bipolar transistor. Further, a pair of diffusion regions 411 and 411' of the p.sup.+ -type is formed in the region 41B, connected with the bridging region 410 which is directly underneath the base 412, as base contact regions. On the region 41B, a doped polysilicon layer is provided to cover the upper major surface of the substrate 41 and patterned to form polysilicon patterns 413A and 413B that are separated from each other at a part of the substrate where the diffusion region 410 is formed. In other words, the surface of the base 412 is exposed at the part where the polysilicon patterns 413A and 413B are separated from each other.
On the polysilicon patterns 413A and 413B, a silicon oxide film 414 is provided as an insulation film that covers the surface of the device except for the base 412, and an emitter electrode 415 of the n.sup.+ -type polysilicon is formed on the silicon oxide film 414 such that the emitter electrode 415 achieves a direct contact with the base 410. Further, contact holes are provided on the silicon oxide film 414 for external connection between an interconnection conductor pattern and the polysilicon patterns 413A, 413B.
In the structure of FIG. 2, one can eliminate the formation of the contact holes for exposing the diffusion regions and the problems associated with the formation of the contact holes, such as the resolution of the contact holes or deviation in the exposure pattern of the contact holes, are eliminated altogether. Thereby, one can reduce the size "d" of the diffusion region as desired. On the other hand, the structure of FIG. 2 has a problem in that the resistance of the electric connection increases inevitably due to the existence of the polysilicon patterns that extend laterally for a relatively long distance between the diffusion region and the low resistance interconnection electrodes. Such a resistance contributes to the time constant of the electric connection system and hence to the undesirable reduction of the operational speed of the device.